DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 462
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 462 of 843
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Section 13 Smart Card Interface
Bit 7
GM
0
1
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 12.2.5,
Serial Mode Register (SMR).
13.2.4
The function of SCR bits 1 and 0 is modified in smart card interface mode.
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 12.2.6,
Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
0
1
Rev. 2.00 Sep 20, 2005 page 422 of 800
REJ09B0260-0200
Bit
Initial value
Read/Write
Serial Control Register (SCR)
Description
Normal smart card interface mode operation
GSM mode smart card interface mode operation
Bit 1
CKE1
0
1
The TEND flag is set 12.5 etu after the beginning of the start bit.
Clock output on/off control only.
The TEND flag is set 11.0 etu after the beginning of the start bit.
Clock output on/off and fixed-high/fixed-low control.
R/W
TIE
7
0
Bit 0
CKE0
0
1
0
1
0
1
R/W
RIE
6
0
Description
Internal clock/SCK pin is I/O port
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at low output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at high output
Internal clock/SCK pin is clock output
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0
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