DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 213
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 213 of 843
- Download datasheet (5Mb)
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a
value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the
P6 7 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be
modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding
bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the
corresponding bit in P6DDR is set to 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Bit
Initial value
Read/Write
Modes 6 and 7 (Single-Chip Mode)
P6
input/output ports. P6
(initial value), and an input port if this bit is set to 1. A pin in port 6 becomes an output port if
the corresponding bit of P6
to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby
mode it retains its previous setting. Therefore, if a transition is made to software standby mode
while port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the
corresponding pin maintains its output state.
7
functions as the clock output pin ( ) or an input port. P6
P6
R
7
1
7
7
is the clock output pin ( ) if the PSTOP bit in MSTCRH is cleared to 0
R/W
P6
6
6
0
DDR to P6
6
R/W
P6
5
0
0
5
DDR is set to 1, and an input port if this pin is cleared
Port 6 data 7 to 0
These bits store data for port 6 pins
R/W
P6
4
0
4
Rev. 2.00 Sep 20, 2005 page 173 of 800
R/W
P6
3
0
3
6
to P6
R/W
P6
2
0
0
function as generic
2
Section 7 I/O Ports
R/W
P6
REJ09B0260-0200
1
0
1
R/W
P6
0
0
0
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