HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 11
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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Item
6.2.3 Page Table
Entry Assistance
Register (PTEA)
7.3.9 Note on Using
Cache Enhanced Mode
8.5.1 Resets
(1) Power-On Reset
(2) Manual Reset
(3) H-UDI Reset
(4) Instruction TLB
Multiple-Hit Exception
(5) Data TLB Multiple-
Hit Exception
8.7.1 Restrictions on
First Instruction in
Exception Handling
Routine
9.1 Features
Figure 9.1 Block
Diagram of INTC
9.2 Input/Output Pins
Table 9.1 Pin
Configuration
Page
124
164 to
166
195
196
197
198
199
220
222
223
Revision (See Manual for Details)
Description amended
When performing access from the CPU in SH7760 to the
PCMCIA interface area with the AT bit in MMUCR cleared to 0,
access is always performed using the values of the
SA and TC bits in this register.
Newly added
Description amended
SR.IMASK = B'1111;
Description amended
SR.IMASK = B'1111;
Description amended
SR.IMASK = B'1111;
Description amended
SR.IMASK = B'1111;
Description amended
SR.IMASK = B'1111;
Note added
•
Note: * See section 31.5, User Break Debug Support Function.
Figure amended
Table amended
Pin Name
IRL interrupt input pins
When the UBDE bit in BRCR is set to 1 and the user break
debug support function* is used, do not locate a BT, BF,
BT/S, BF/S, BRA, or BSR instruction at the address
indicated by DBR.
Interrupt
request
IMASK
SR
CPU
Abbreviation
IRL3 to IRL0
Rev. 2.00 Feb. 12, 2010 Page ix of lxxxii
I/O
Input
Input of IRL interrupt request signals
(maskable by the IMASK bits in SR)
Function
REJ09B0554-0200
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