HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 235
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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7.1
This LSI has an on-chip 16-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte
operand cache (OC) for data. Half of the memory of the operand cache (16 Kbytes) may
alternatively be used as on-chip RAM. When the EMODE bit in CCR is 0, this LSI's cache
behaves as shown in table 7.1. The features of the cache when the EMODE bit in CCR is 1 are
given in table 7.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset.
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. The features of the store queues are given in table 7.3.
Table 7.1
Item
Capacity
Type
Line size
Entries
Write method
Table 7.2
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Features
Cache Features (EMODE = 0)
Cache Features (EMODE = 1)
Instruction Cache
8-Kbyte cache
Direct mapping
32 bytes
256 entires
⎯
Instruction Cache
16-Kbyte cache
2-way set-associative
32 bytes
256 entries/way
⎯
LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Section 7 Caches
Rev. 2.00 Feb. 12, 2010 Page 151 of 1330
Operand Cache
16-Kbyte cache or
8-Kbyte cache + 8-Kbyte RAM
Direct mapping
32 bytes
512 entires
Copy-back/write-through selectable
Operand Cache
32-Kbyte cache or
16-Kbyte cache + 16-Kbyte RAM
2-way set-associative
32 bytes
512 entries/way
Copy-back/write-through selectable
REJ09B0554-0200
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