HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 856
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Company:
Part Number:
HD6417760BL200AV
Manufacturer:
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21.3.21 Root Hub Status Register (HcRhStatus)
HcRhStatus is divided into two parts. The high-order word in a longword represents the hub status
change bits and the low-order word in a longword represents the hub status bits.
Since this register functions differently in read than in write, functional descriptions will be made
separately below. Note that bit titles in read are different from those in write so that bit titles can
always suit the functions. For the bit name, the bit title for a read operation is used. Taking bit 0 as
an example, the bit name is LPS and the bit title in read is Local Power Status while that in write
is Clear Global Power.
• Read
Initial value:
Initial value:
Bit
31
30 to 18
17
16
15
Rev. 2.00 Feb. 12, 2010 Page 772 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
CRWE
DRWE
Bit Name
CRWE
⎯
OCIC
LPSC
DRWE
31
15
R
R
0
0
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
0
All 0
0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
26
10
R
R
-
0
-
0
R/W
R
R
R
R
R
25
R
R
-
0
9
-
0
Description
Reserved
These bits are always read as 0.
Reserved
These bits are always read as 0.
Overcurrent Indicator Change
This bit is set to 1 by hardware when a change has
occurred to the OCI bit of this register.
0: Operation is not affected
1: Overcurrent indicator has changed
Local Power Status Change
The root hub does not support the local power
status function, thus, this bit is always read as 0.
Device Remote Wakeup Enable
When this bit is 1, the CSC bit is enabled as a
resume event, causing a USB suspend to USB
resume state transition and setting the RD interrupt.
0: Does not generate device remote wakeup event
1: Generates device remote wakeup event
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
22
R
R
0
0
6
-
-
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
19
R
R
0
3
0
-
-
18
R
R
0
2
0
-
-
OCIC
OCI
17
R
R
0
1
0
LPSC
LPS
16
R
R
0
0
0
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