HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 207
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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6.2.2
PTEL can be accessed in longwords from H'FF00 0004 in the P4 area and from H'1F00 0004 in
area 7. PTEL is used to hold the physical page number and page management information to be
recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not
changed unless a software directive is issued.
Initial value:
Initial value:
Bit
31 to 10 VPN
9, 8
7 to 0
Bit
31 to 29 ⎯
28 to 10 PPN
9
8
7
6
5
4
3
2
1
0
R/W:
R/W:
Bit:
Bit:
Page Table Entry Low Register (PTEL)
Bit Name
⎯
ASID
Bit Name
⎯
V
SZ1
PR1
PR0
SZ0
C
D
SH
WT
R/W
31
15
R
0
-
-
R/W
30
14
-
R
0
-
R/W
29
13
R
0
-
-
PPN
Initial Value
⎯
All 0
⎯
Initial Value
All 0
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
28
12
-
-
R/W
R/W
27
11
-
-
R/W
R/W
26
10
-
-
R/W
R/W
R
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
25
0
R
-
9
-
Description
Virtual Page Number
Reserved
These bits are always read as 0. The write value
should always be 0.
Address Space Identifier
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Physical Page Number
Reserved
This bit is always read as 0. The write value
should always be 0.
Page Management Information
For details, see section 6.3, TLB Functions.
R/W
R/W
24
V
8
-
-
R/W
R/W
SZ1
23
7
-
-
PPN
Rev. 2.00 Feb. 12, 2010 Page 123 of 1330
R/W
PR1
R/W
22
6
-
-
R/W
R/W
PR0
21
5
-
-
R/W
R/W
SZ0
20
4
-
-
R/W
R/W
19
3
C
-
-
REJ09B0554-0200
R/W
R/W
18
2
D
-
-
R/W
R/W
SH
17
1
-
-
R/W
R/W
WT
16
0
-
-
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