HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 262
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Company:
Part Number:
HD6417760BL200AV
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7.6.5
The address ranges to which the OC is memory-mapped in double-size cache mode of this LSI are
summarized below in the example of data array access.
• In normal mode (ORA = 0 in CCR)
• In RAM mode (ORA = 1 in CCR)
7.7
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. If the SQs are not used, power-down modes, in which SQ functions are stopped, can be
used to reduce power consumption. The queue address control registers (QACR0 and QACR1)
cannot be accessed while SQ functions are stopped. See section 14, Power-Down Modes, for the
procedure for stopping SQ functions.
7.7.1
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 7.13. These two store
queues can be set independently.
Rev. 2.00 Feb. 12, 2010 Page 178 of 1330
REJ09B0554-0200
H'F500 0000 to H'F500 3FFF (16 Kbytes ): Way 0 (entries 0 to 511)
H'F500 4000 to H'F500 7FFF (16 Kbytes ): Way 1 (entries 0 to 511)
In the same pattern, shadows of the cache area are created in 32-Kbyte blocks until H'F5FF
FFFF.
H'F500 0000 to H'F500 1FFF (8 Kbytes ): Way 0 (entries 0 to 255)
H'F500 2000 to H'F500 3FFF (8 Kbytes ): Way 1 (entries 0 to 255)
In the same pattern, shadows of the cache area are created in 16-Kbyte blocks until H'F5FF
FFFF.
Summary of Memory-Mapping of OC
Store Queues
SQ Configuration
SQ0
SQ1
SQ0[0]
SQ1[0]
4 bytes
Figure 7.13 Store Queue Configuration
SQ0[1]
SQ1[1]
4 bytes
SQ0[2]
SQ1[2]
4 bytes
SQ0[3]
SQ1[3]
4 bytes
SQ0[4]
SQ1[4]
4 bytes
SQ0[5]
SQ1[5]
4 bytes
SQ0[6]
SQ1[6]
4 bytes
SQ0[7]
SQ1[7]
4 bytes
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