UPD78F9201MA-CAC-A Renesas Electronics America, UPD78F9201MA-CAC-A Datasheet - Page 337

• Manufacturer Part Number: UPD78F9201MA-CAC-A
• Description: MCU 8BIT 2KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9201MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Flash
memory
Function
Self
programming
function
FLPMC: Flash
programming
mode control
register
PFCMD: Flash
protect
command
register
PFS: Flash
status register
FLAPH, FLAPL:
Flash address
pointers H and
L
FLAPHC,
FLAPLC: Flash
address pointer
H/L compare
registers
Shifting to self
programming
mode
Shifting to
normal mode
Byte write
Details of
Function
The state of the pins in self programming mode is the same as that in HALT
mode.
Since the security function set via on-board/off-board programming is disabled in
self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase processing
during self programming, set the protect byte.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command, there is a possibility that device does not operate normally.
Clear the value of the FLCMD register to 00H immediately before setting self-
programming mode and normal operation mode.
Cautions in the case of setting the self programming mode, refer to 16.8.2
Cautions on self programming function.
Set the CPU clock so that it is 1 MHz or more during self programming.
Execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, then execute self programming. At this
time, the HALT instruction is automatically released after 10
clocks (f
If the clock of the oscillator or an external clock is selected as the system clock,
execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, wait for 8
status, and then execute self programming.
Clear the value of the FLCMD register to 00H immediately before setting self
programming mode and normal operation mode.
Interrupt servicing cannot be executed in self-programming mode. Disable
interrupt servicing (by executing the DI instruction while MK0 = FFH) before
executing the specific sequence that sets self-programming mode and after
executing the specific sequence that changes the mode to the normal mode.
Check FPRERR using a 1-bit memory manipulation instruction.
Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
Set the number of the block subject to a block erase, verify, or blank check (same
value as FLAPH) to FLAPHC.
Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank
check is performed.
Be sure to perform the series of operations described above using the user
program at an address where data is not erased or written.
If a write results in failure, erase the block once and write to it again.
CPU
APPENDIX D LIST OF CAUTIONS
).
User’s Manual U18172EJ3V0UD
Cautions
μ
s after releasing the HALT
μ
s (MAX.) + 2 CPU
p. 238
245, 247,
248
p. 237
p. 237
p. 237
p. 237
p. 238
p. 238
p. 238
p. 238
p. 239
p. 239
p. 242
pp. 244,
p. 242
p. 242
p. 242
p. 256
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