UPD78F9201MA-CAC-A Renesas Electronics America, UPD78F9201MA-CAC-A Datasheet - Page 40

• Manufacturer Part Number: UPD78F9201MA-CAC-A
• Description: MCU 8BIT 2KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9201MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

38
(3) Stack pointer (SP)
SP
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack
area).
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Caution 1.
SP15
15
SP
SP
SP14
2.
SP _ 2
SP _ 2
SP _ 1
SP + 1
SP + 2
SP
SP
Since reset signal generation makes the SP contents undefined, be sure to initialize the
SP before using the stack memory.
Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can
be actually set.
0FF00H is in the SFR area, not the high-speed RAM area, so it was converted to 0FB00H
that is in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become
0FAFFH, but that value is not in the high-speed RAM area, so it is converted to 0FEFFH,
which is the same value as when 0FF00H is set to the stack pointer.
SP13 SP12 SP11 SP10 SP9
Lower half
register pairs
Upper half
register pairs
Lower half
register pairs
Upper half
register pairs
POP rp
instruction
PUSH rp
instruction
Figure 3-11. Data to Be Restored from Stack Memory
Figure 3-10. Data to Be Saved to Stack Memory
Figure 3-9. Stack Pointer Configuration
CHAPTER 3 CPU ARCHITECTURE
SP
SP
User’s Manual U18172EJ3V0UD
SP _ 2
SP _ 2
SP _ 1
SP + 1
SP + 2
SP
SP
SP8
RET instruction
PC15 to PC8
PC15 to PC8
PC7 to PC0
CALL, CALLT
instructions
PC7 to PC0
SP7
SP6
SP5
SP
SP
SP _ 3
SP _ 3
SP _ 2
SP _ 1
SP4
SP + 1
SP + 2
SP + 3
SP
SP
SP3
RETI instruction
PC15 to PC8
PC15 to PC8
PC7 to PC0
PC7 to PC0
SP2
Interrupt
PSW
PSW
SP1
SP0
0