UPD78F9201MA-CAC-A Renesas Electronics America, UPD78F9201MA-CAC-A Datasheet - Page 86
UPD78F9201MA-CAC-A
Manufacturer Part Number
UPD78F9201MA-CAC-A
Description
MCU 8BIT 2KB FLASH 128B RAM
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9500MA-CAC-A.pdf
(342 pages)
Specifications of UPD78F9201MA-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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(2) Crystal/ceramic oscillator ( PD78F920x only)
84
Notes 1. Operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.).
If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected
and the accuracy of processing is improved because the frequency deviation is small, as compared with high-
speed internal oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
(b) After high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
referenced after reset, and the system clock is selected.
selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator ( PD78F920x Only)
2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to
Internal reset
System clock
CPU clock
released is selected by the oscillation stabilization time select register (OSTS).
CHAPTER 15 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is
RESET
V
DD
H
(a)
System clock is selected.
(Operation stops
CHAPTER 5 CLOCK GENERATORS
Option byte is read.
User’s Manual U18172EJ3V0UD
Note 1
)
(b)
Clock oscillation
stabilization
time
Note 2
(c)
PCC = 02H, PPCC = 02H
Crystal/ceramic
oscillator clock
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