UPD78F9202MA-CAC-A Renesas Electronics America, UPD78F9202MA-CAC-A Datasheet - Page 131

• Manufacturer Part Number: UPD78F9202MA-CAC-A
• Description: MCU 8BIT 4KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9202MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

(18) Edge detection
(19) External event counter
(20) PPG output
(21) STOP mode or system clock stop mode setting
(22) P21/TI010/TO00 pin
<1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
<2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and
<1> The timing of the count start is after two valid edge detections.
<2> When reading the external event counter count value, TM00 should be read.
<1> Values in the following range should be set in CR000 and CR010:
<2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010
Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before setting STOP
mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts.
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).
When using P21 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge.
Remark n = 0, 1
when it is used as a capture trigger. In the former case, the count clock is f
count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short
pulse width.
0000H < CR010 < CR000
setting value + 1)/(CR000 setting value + 1).
(a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit
(b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled
(c) When the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then
after a low level is input to the TI0n0 pin
enabled after a high level is input to the TI0n0 pin
timer counter 00 (TM00) is enabled
If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a falling edge is detected immediately after the TM00 operation is enabled.
If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ( PD78F920x ONLY)
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User’s Manual U18172EJ3V0UD
XP
, and in the latter case the
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