UPD78F9202MA-CAC-A Renesas Electronics America, UPD78F9202MA-CAC-A Datasheet - Page 165

• Manufacturer Part Number: UPD78F9202MA-CAC-A
• Description: MCU 8BIT 4KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9202MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 s or longer to stabilize the
Cautions 1.
Notes 3. Set the sampling time as follows.
internal circuit.
2.
3.
4.
ADCS
Comparator
0
0
1
4. Set the A/D conversion time as follows.
5. Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4.
6. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1
The above sampling time and conversion time do not include the clock frequency error.
Select the sampling time and conversion time such that Notes 3 and 4 above are satisfied,
while taking the clock frequency error into consideration (an error margin maximum of 5%
when using the high-speed internal oscillator).
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
Be sure to clear bits 6, 2, and 1 to 0.
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the
first conversion result. If the ADCS is set to 1 without waiting for 1 s or longer, ignore the first
conversion data.
ADCE
ADCS
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
ADCE
0
1
4.5 V:
4.0 V:
2.85 V:
2.7 V:
4.5 V:
4.0 V:
2.85 V:
2.7 V:
Figure 9-4. Timing Chart When Comparator Is Used
Note
CHAPTER 9 A/D CONVERTER ( PD78F920x ONLY)
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only comparator consumes power)
Conversion mode
Table 9-2. Settings of ADCS and ADCE
Conversion
operation
1.0 s or more
2.4 s or more
3.0 s or more
11.0 s or more
3.0 s or more and less than 100 s
4.8 s or more and less than 100 s
6.0 s or more and less than 100 s
14.0 s or more and less than 100 s
Comparator operating
User’s Manual U18172EJ3V0UD
Conversion
waiting
A/D Conversion Operation
Conversion
operation
Conversion stopped
s from
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