UPD78F9202MA-CAC-A Renesas Electronics America, UPD78F9202MA-CAC-A Datasheet - Page 331

• Manufacturer Part Number: UPD78F9202MA-CAC-A
• Description: MCU 8BIT 4KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9202MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

A/D
converter
(
20x only)
Function
μ
PD78F9
ADM: A/D
converter mode
register
ADS: Analog
input channel
specification
register
ADCR: 10-bit
A/D conversion
result register
PMC2: Port
mode control
register 2
A/D converter
operations
Operating
current in STOP
mode
Input range of
ANI0 to ANI3
Conflicting
operations
Details of
Function
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped
(ADCS = 0) and then A/D conversion is started, execute two NOP instructions or
an instruction equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
Be sure to clear bits 6, 2, and 1 to 0.
Be sure to clear bits 2 to 7 of ADS to 0.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion result
to be read.
If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1,
P21/ANI1/TIO10/TO00/INTP0, P22/ANI2, and P23/ANI3 pins cannot be used for
any purpose other than the A/D converter function.
Be sure to set 0 to the Pull-up resistor option register of the pin set in A/D
converter mode.
Make sure the period of <1> to <4> is 1
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, ignore the data resulting from the first conversion
after <4> in this case.
The period from <5> to <8> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set
using FR2 to FR0.
To satisfy the DC characteristics of supply current in STOP mode, clear bit 7
(ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before
executing the STOP instruction.
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of V
higher and V
to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
Conflict between A/D conversion result register (ADCR, ADCRH) write and
ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH
read has priority. After the read operation, the new conversion result is written to
ADCR, ADCRH.
Conflict between ADCR, ADCRH write and A/D converter mode register (ADM)
write or analog input channel specification register (ADS) write upon the end of
conversion ADM or ADS write has priority. ADCR, ADCRH write is not
performed, nor is the conversion end interrupt signal (INTAD) generated.
APPENDIX D LIST OF CAUTIONS
SS
User’s Manual U18172EJ3V0UD
or lower (even in the range of absolute maximum ratings) is input
Cautions
μ
s or more.
DD
or
pp. 166,
170
pp. 166,
170
p. 163
p. 163
p. 163
p. 164
p. 164
p. 165
p. 170
p. 170
p. 173
p. 173
p. 173
p. 173
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