UPD78F9202MA-CAC-A Renesas Electronics America, UPD78F9202MA-CAC-A Datasheet - Page 45

• Manufacturer Part Number: UPD78F9202MA-CAC-A
• Description: MCU 8BIT 4KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9202MA-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 7
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

<R>
Notes 1.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S,
FFA9H to
FFE1H to
FFE5H to
to FFF2H
FFF5H to
Address
FFDFH
FFEBH
FFECH
FFEDH
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA5H
FFA6H
FFA7H
FFA8H
FFE0H
FFE3H
FFE4H
FFF3H
FFF4H
FFFAH
FFFBH
2. The oscillation stabilization time that elapses after release of reset is selected by the option byte. For
FLAPHC
PFCMD
PFS
FLPMC
FLCMD
FLAPL
FLAPH
FLAPLC
FLW
IF0
MK0
INTM0
PPCC
OSTS
Note 1
PCC
Symbol
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S.
μ
details, refer to CHAPTER 15 OPTION BYTE.
PD78F920x only
−
−
−
−
−
<ADIF>
<ADM
REG7
FLW7
FLAP
Note 1
Note 1
FLA
P7
C7
K>
7
0
0
0
0
0
−
−
−
0
−
0
0
−
0
PRSEL
<TMIF
<TMM
K010>
REG6
FLW6
FLAP
010>
FLA
Note 1
Note 1
F4
P6
C6
6
0
0
0
0
−
−
−
0
−
0
0
−
0
PRSEL
<TMIF
<TMM
K000>
REG5
FLW5
FLAP
ES11
000>
Note 1
Note 1
FLA
F3
P5
C5
5
0
0
0
0
−
−
−
−
0
0
−
0
Table 3-3. Special Function Registers (3/3)
PRSEL
<TMIF
REG4
<TMM
FLW4
KH1>
ES10
FLAP
FLA
H1>
CHAPTER 3 CPU ARCHITECTURE
P4
F2
C4
4
0
0
0
0
−
−
−
−
0
0
−
0
Bit No.
User’s Manual U18172EJ3V0UD
PRSEL
<PIF1> <PIF0> <LVIIF>
REG3
<PMK
FLW3
ES01
FLAP
FLAP
FLA
FLA
P11
C11
P3
C3
F1
1>
3
0
0
−
−
−
−
0
0
−
0
PRSEL
REG2
WEPR
FLCM
<PMK
FLW2
ES00
FLAP
FLAP
ERR
FLA
FLA
P10
C10
F0
D2
P2
C2
0>
2
−
−
−
−
0
0
−
0
PPCC1 PPCC0
OSTS1 OSTS0
REG1
FLCM
FLW1
PCC1
FLAP
FLAP
VCE
<LVI
MK>
FLA
FLA
RR
D1
P1
P9
C9
C1
1
0
−
−
−
0
−
−
FLCMD
FLSPM
REG0
FLW0
FLAP
FLAP
ERR
FPR
FLA
FLA
P0
P8
C8
C0
0
0
−
0
−
1
−
0
−
−
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
−
−
−
−
−
1
−
√
−
√
√
√
√
√
−
−
√
−
√
−
−
−
√
−
−
√
Simultaneously
Number of Bits
Manipulated
8
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
−
√
16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Undefined
Undefined
Undefined
Note 2
00H
00H
00H
00H
00H
00H
FFH
00H
02H
02H
Reset
After
−
−
−
−
−
78, 188
239
239
238
241
242
242
243
179
180
180
76
76
−
−
−
−
−
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