UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 192

• Manufacturer Part Number: UPD78F9234MC-5A4-A
• Description: MCU 8BIT 8KB FLASH 30PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9234MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

190
Notes 1.
Caution
Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
2.
3.
1. At startup, transmission operation is started by setting TXE6 to 1 after having set POWER6 to
TXE6 is synchronized by the base clock (f
operation, set TXE6 to 1 after having set TXE6 to 0 and one clock of the base clock (f
elapsed. If TXE6 is set to 1 before one clock of the base clock (f
circuit may not able to be initialized.
RXE6 is synchronized by the base clock (f
set RXE6 to 1 after having set RXE6 to 0 and one clock of the base clock (f
RXE6 is set to 1 before one clock of the base clock (f
be able to be initialized.
If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous
serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not
occur.
RXE6
TXE6
ISRM6
PS61
CL6
1, then setting the transmit data to TXB6 after having waited for one clock or more of the
base clock (f
TXE6 to 0.
SL6
0
1
0
1
0
0
1
1
0
1
0
1
0
1
Note 1
Note 2
Disable transmission (synchronously reset the transmission circuit).
Enable transmission
Disable reception (synchronously reset the reception circuit).
Enable reception
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
PS60
XCLK6
0
1
0
1
). When stopping transmission operation, set POWER6 to 0 after having set
Enabling/disabling occurrence of reception completion interrupt in case of error
CHAPTER 11 SERIAL INTERFACE UART6
Parity bit not output.
Output 0 parity.
Output odd parity.
Output even parity.
User’s Manual U17446EJ5V0UD
Specification of character length of transmit/receive data
Transmission operation
Specification of number of stop bits of transmit data
Enabling/disabling transmission
XCLK6
Enabling/disabling reception
XCLK6
) set by CKSR6. When re-enabling reception operation,
) set by CKSR6. When re-enabling transmission
XCLK6
) has elapsed, the reception circuit may not
Reception without parity
Reception as 0 parity
Judge as odd parity.
Judge as even parity.
XCLK6
) has elapsed, the transmission
Reception operation
XCLK6
Note 3
) has elapsed. If
XCLK6
) has