UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 292
UPD78F9234MC-5A4-A
Manufacturer Part Number
UPD78F9234MC-5A4-A
Description
MCU 8BIT 8KB FLASH 30PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9232MC-5A4-A.pdf
(419 pages)
Specifications of UPD78F9234MC-5A4-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
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UPD78F9234MC-5A4-A
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Manufacturer:
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(5) Flash address pointers H and L (FLAPH and FLAPL)
(6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and
FLAPLC)
These registers are used to specify the start address of the flash memory when the memory is erased, written,
or verified in the self programming mode.
FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of
FLAPHC and FLAPLC when the programming command is not executed. When the programming command
is executed, therefore, set the value again.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation makes these registers undefined.
These registers are used to specify the address range in which the internal sequencer operates when the flash
memory is verified in the self programming mode.
Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to
be executed to FLAPLC.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Caution Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the self
Figure 19-15. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC)
Cautions 1. Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the self
Address: FFA4H, FFA5H
Address: FFA6H, FFA7H
0
0
0
0
programming command. If the self programming command is executed with these bits
set to 1, the device may malfunction.
2. Set the number of the block subject to a block erase, verify, or blank check (same
3. Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank check is
Figure 19-14. Format of Flash Address Pointers H/L (FLAPH/FLAPL)
programming command. If the self programming command is executed with these bits
set to 1, the device may malfunction.
value as FLAPH) to FLAPHC.
performed.
0
0
FLAPHC (FFA7H)
FLAPH (FFA5H)
FLAP
FLA
P12
C12
FLAP
FLA
P11
C11
After reset: Undefined
After reset: 00H
FLAP
FLA
P10
C10
CHAPTER 19 FLASH MEMORY
User’s Manual U17446EJ5V0UD
FLAP
FLA
P9
C9
FLAP
FLA
P8
C8
R/W
FLAP
FLA
P7
C7
R/W
FLAP
FLA
P6
C6
FLAP
FLA
P5
C5
FLAPLC (FFA6H)
FLAPL (FFA4H)
FLAP
FLA
P4
C4
FLAP
FLA
P3
C3
FLAP
FLA
P2
C2
FLAP
FLA
P1
C1
FLAP
FLA
P0
C0
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