MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 33

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

T2CNA.6: T2OE0
T2CNA.7: ET2
T2H (01h, 02h)
Initialization:
Read/Write Access:
T2H.[7:0]:
T2RH (02h, 02h)
Initialization:
Read/Write Access:
T2RH.[7:0]:
T2CH (03h, 02h)
Initialization:
Read/Write Access:
T2CH.[7:0]:
PO2 (04h, 02h)
Initialization:
Read/Write Access:
PO2.[6:0]:
PO2.7: Reserved
______________________________________________________________________________________
Low-Power, Dual-Core Microcontroller
Timer 2 Output Enable 0. This register bit enables the timer 2 output function for the external T2P
pin. The table below shows timer 2 output possibilities for the T2P, T2PB pins.
Enable Timer 2 Interrupts. This bit serves as the local enable for timer 2 interrupt sources that fall
under the TF2 and TCC2 interrupt flags.
Timer 2 Most Significant Byte
The timer 2 most significant byte is cleared to 00h on all forms of reset.
Unrestricted read/write.
Timer 2 MSB Bits 7:0. This register is used to load and read the most significant 8-bit value in timer 2.
Timer 2 Most Significant Byte Reload
The timer 2 most significant byte is cleared to 00h on all forms of reset.
Unrestricted read/write.
Timer 2 Reload MSB Bits 7:0. This register is used to load and read the most significant 8-bit
value in timer 2.
Timer 2 Most Significant Byte Capture/Compare
This byte is cleared to 00h on all forms of reset.
Unrestricted read/write.
Timer 2 Capture/Compare MSB Bits 7:0. This register reflects the upper byte of the timer 2
capture/compare value and is read/write accessible at all times.
Port 2 Output Register (8-Bit Register)
This register is set to 1Fh on all forms of reset.
Unrestricted read/write.
Port 2 Output Register Bits 6:0. The PO2 register stores output data for port 2 when it is defined as
an output port and controls whether the internal weak p-channel pullup transistor is
enabled/disabled if a port pin is defined as an input. The contents of this register can be modified
by a write access. Reading from the register returns the contents of the register. Changing the
direction of port 2 does not change the data contents of the register.
Reserved. Reads return 0.
Special Function Register Bit Descriptions (continued)
T20E[1:0]
00
01
10
11
01
10
11
T2MD
X
0
0
0
1
1
1
8-bit PWM output (T2H)
8-bit PWM output (T2H)
16-bit PWM output
16-bit PWM output
Port latch data
Port latch data
Port latch data
T2P PIN
8-bit PWM output (T2L)
8-bit PWM output (T2L)
16-bit PWM output
16-bit PWM output
Port latch data
Port latch data
Port latch data
T2PB PIN
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