MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 34

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual-Core Microcontroller
34
PI2 (05h, 02h)
Initialization:
Read/Write Access:
PI2.[6:0]:
PI2.7: Reserved
SCON0 (06h, 02h)
Initialization:
Read/Write Access:
SCON0.0: RI
SCON0.1: TI
SCON0.2: RB8
SCON0.3: TB8
SCON0.4: REN
SCON0.5: SM2
SCON0.6: SM1
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Port 2 Input Register
The reset value for this register is dependent on the logical states of the pins.
Unrestricted read-only.
Port 2 Input Register Bits 6:0. The PI2 register always reflects the logic state of its pins when read.
Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel
pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is
on; if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-state.
Reserved. Reads return 0.
Serial Port 0 Control Register
The serial port control is cleared to 00h on all forms of reset.
Unrestricted read/write.
Receive Interrupt Flag. This bit indicates that a data byte has been received in the serial port
buffer. The bit is set at the end of the 8th bit for mode 0, after the last sample of the incoming stop
bit for mode 1 subject to the value of the SM2 bit, or after the last sample of RB8 for modes 2 and
3. This bit must be cleared by software once set.
Transmit Interrupt Flag. This bit indicates that the data in the serial-port data buffer has been
completely shifted out. It is set at the end of the last data bit for all modes of operation and must
be cleared by software once set.
9th Received Bit State. This bit identifies the state of the 9th bit of received data in serial port
modes 2 and 3. When SM2 is 0, it is the state of the stop bit in mode 1. This bit has no meaning in
mode 0.
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port
modes 2 and 3.
Receive Enable
Serial Port 0 Mode Bit 2. Setting this bit in mode 1 ignores reception if an invalid stop bit is
detected. Setting this bit in mode 2 or 3 enables multiprocessor communications, and prevents the
RI bit from being set and the interrupt from being asserted if the 9th bit received is 0. This bit is
also used to support mode 0 for clock selection.
Serial Port 0 Mode Bit 1
REN_0 = 0: Serial port 0 receiver disabled.
REN_0 = 1: Serial port 0 receiver enabled for modes 1, 2 and 3. Initiate synchronous reception for
mode 0.
SM2 = 0: clock is divided by 12
SM2 = 1: clock is divided by 4
Special Function Register Bit Descriptions (continued)