MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 39

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCNT.2: MSUB
MCNT.3: OPCS
MCNT.4: SQU
MCNT.5: CLD
MCNT.6: MCW
MCNT.7: OF
MCNT.8: Reserved
MCNT.[15:9]: Reserved
MA (01h, 03h)
Initialization:
Read/Write Access:
MA.[15:0]:
______________________________________________________________________________________
Low-Power, Dual-Core Microcontroller
Multiply-Accumulate Negate. The state of the MSUB and MMAC bits determines the operation of
the hardware multiplier. The accumulator MC is formed by the MC2, MC1, and MC0 registers.
Operand Count Select. This bit is used to select a number of operands for the multiplication
operation. When this bit is cleared to logic 0, an operation is initiated after two operands are written
to the MA and MB registers. When this bit is set to logic 1, an operation is initiated after an
operand is written to either the MA or the MB register. This bit has no meaning if the SQU bit is set.
This bit has no effect on division.
Square-Function Enable. This bit is used to support hardware square function. When this bit is set
to logic 1, a square operation is initiated after an operand is written to either the MA or the MB
register. Writing data to either of the operand registers writes to both registers and triggers a square
calculation. Setting this bit to 1 also disables the OPCS function. When this bit is cleared to logic
0, the hardware square function is disabled. This bit has no effect on division.
Clear Data Register. This bit is used to initialize the operand registers and the accumulator of the
multiplier. The contents of all five data registers and the OF bit are cleared to 0 and the sequence
counter is reset immediately after the CLD is set. This bit is cleared by hardware automatically. If
an operation is in progress (DIVSZ = 1) when this bit is set to 1, the operation is aborted and the
contents of all data registers and the OF bit are cleared to 0. Writing this bit to 0 causes no
operation.
MC Register Write Select. The state of the MCW bit determines if a multiplication operation result
is placed into the accumulator register (MC):
Overflow Flag. This bit is set to logic 1 when an overflow occurred for the last operation. This bit is
automatically cleared to 0 following a reset, starting a multiplier/division operation or the setting of
the CLD bit to 1.
Reserved. Do not write a 1 to this location. Functionally, this is the DIVE bit, however, there are
problems with the divide operation.
Reserved. Reads return 0.
Multiplier Operand A Register
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Multiplier Operand A Bit 15:0. This operand A register is used by the user software to load a 16-bit
value for a multiplier operation. Loading of the MA and MB registers initiates a selected multiplier
operation, dependent on the setting of the MMAC bit. The data type is determined by the SUS bit.
The result is stored to the MC register.
If MCW is 0, the result is written to the MC register.
If MCW is 1, the result is not placed into the MC register and the content of the MC register is not
changed. This bit has no effect on division.
Special Function Register Bit Descriptions (continued)
MSUB
0
0
1
1
MMAC
0
1
0
1
MC + (MA x MB)
MC - (MA x MB)
OPERATION
- (MA x MC)
MA x MB
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