AT89C5132-ROTIL Atmel, AT89C5132-ROTIL Datasheet - Page 53

• Manufacturer Part Number: AT89C5132-ROTIL
• Description: IC 8051 MCU FLASH 64K USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-ROTIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

12.4.1
12.4.2
12.4.3
12.4.4
12.5
Figure 12-10. Timer Interrupt System
4173E–USB–09/07
Interrupt
Mode 0 (13-bit Timer)
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with
Auto-Reload)
Mode 3 (Halt)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register)
with a modulo-32 prescaler implemented with the lower 5 Bits of the TL1 register (see Figure 12-
2). The upper 3 Bits of TL1 register are ignored. Prescaler overflow increments TH1 register.
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade
(see Figure 12-4). The selected input increments TL1 register.
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 reg-
ister on overflow (see Figure 12-6). TL1 overflow sets TF1 flag in TCON register and reloads
TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1
when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is
set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt rou-
tine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
TCON.5
TCON.7
TF0
TF1
IEN0.1
IEN0.3
ET0
ET1
Timer 0
Interrupt Request
Timer 1
Interrupt Request
AT89C5132
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