AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 198
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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17.11.8
198
AT90CAN32/64/128
USART1 Control and Status Register C – UCSR1C
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, these bit must be written
to zero when UCSRnC is written.
• Bit 6 – UMSELn: USARTn Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 17-4.
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 17-5.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 17-6.
Bit
Read/Write
Initial Value
UPMn1
UMSELn
0
0
1
1
0
1
UMSELn Bit Settings
UPMn Bits Settings
USBSn Bit Settings
USBSn
R
7
–
0
0
1
UMSEL1
R/W
6
0
UPMn0
Mode
Asynchronous Operation
Synchronous Operation
UPM11
0
1
0
1
R/W
5
0
UPM10
Stop Bit(s)
1-bit
2-bit
R/W
4
0
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
USBS1
R/W
3
0
UCSZ11
R/W
2
1
UCSZ10
R/W
1
1
UCPO1L
R/W
0
0
UCSR1C
7679H–CAN–08/08
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