AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 220

• Manufacturer Part Number: AT90CAN128-16MJ
• Description: IC MCU AVR FLASH 128K 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-16MJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• For Use With: ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 18-3.
220
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x18
0x20
0x28
0x30
0x38
AT90CAN32/64/128
Status of the Two-wire Serial Bus
and Two-wire Serial Interface
Hardware
A START condition has been
transmitted
A repeated START condition has
been transmitted
SLA+W has been transmitted;
ACK has been received
SLA+W has been transmitted;
NOT ACK has been received
Data byte has been transmitted;
ACK has been received
Data byte has been transmitted;
NOT ACK has been received
Arbitration lost in SLA+W or data
bytes
Status Codes for Master Transmitter Mode
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the
same slave again, or a new slave without transmitting a STOP condition. Repeated START
enables the master to switch between slaves, Master Transmitter mode and Master Receiver
mode without losing control of the bus.
To/from TWDR
Load SLA+W
Load SLA+W or
Load SLA+R
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
Application Software Response
To TWCR
STA
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
STO
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWEA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by TWI Hardware
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to master receiver mode
Data byte will be transmitted and ACK or NOT ACK will be
received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Data byte will be transmitted and ACK or NOT ACK will be
received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Data byte will be transmitted and ACK or NOT ACK will be
received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Data byte will be transmitted and ACK or NOT ACK will be
received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Two-wire Serial Bus will be released and not addressed
slave mode entered
A START condition will be transmitted when the bus be-
comes free
7679H–CAN–08/08