AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 30
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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AT90CAN32/64/128
address actually is driven on the bus. The access time cannot exceed the time from the ALE
pulse must be asserted low until data is stable during a read sequence (see t
in
tional feature, it is possible to divide the external memory space in two sectors with individual
wait-state settings. This makes it possible to connect two different memory devices with different
timing requirements to the same XMEM interface. For XMEM interface timing details, please
refer to
Memory Characteristics” on page
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 4-6.
Note:
Figure 4-7.
Table 26-7
Table 26-7
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
System Clock (CLK
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
through
External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)
External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
through
DA7:0
A15:8
CPU
ALE
WR
Table
RD
)
Prev. addr.
Prev. data
Prev. data
Prev. data
DA7:0
A15:8
CPU
ALE
WR
RD
26-14). The different wait-states are set up in software. As an addi-
Table 26-14
)
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
375.
T1
and
Address
Address
Address
T2
Figure 26-6
Address
Address
Address
XX
T2
XX
XXXXX
Address
T3
Data
Data
Data
to
Figure 26-9
Address
T3
Data
Data
Data
T4
XXXXXXXX
in the
T4
LLRL
(1)
“External Data
+ t
T5
7679H–CAN–08/08
RLRH
(1)
- t
DVRH
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