AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 96
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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11. Timer/Counter3/1/0 Prescalers
11.1
11.1.1
11.1.2
11.1.3
96
Overview
AT90CAN32/64/128
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to both
Timer/Counter3, Timer/Counter1 and Timer/Counter0.
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1 and Timer/Counter0. Since
the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of prescaling arti-
facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T3/T1/T0 pin can be used as Timer/Counter clock
(clk
chronization logic. The synchronized (sampled) signal is then passed through the edge detector.
Figure 11-1
edge detector logic. The registers are clocked at the positive edge of the internal system clock
(
The edge detector generates one clk
tive (CSn2:0 = 6) edge it detects.
CLK_I/O
clk
I/O
T3
). The latch is transparent in the high period of the internal system clock.
/clk
/1024.
T1
/clk
shows a functional equivalent block diagram of the T3/T1/T0 synchronization and
T0
). The T3/T1/T0 pin is sampled once every system clock cycle by the pin syn-
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a
T3
/clk
T1
/clk
T0
pulse for each positive (CSn2:0 = 7) or nega-
CLK_I/O
/8, f
CLK_I/O
/64, f
7679H–CAN–08/08
CLK_I/O
/256, or
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