AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 32
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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4.5.6
32
AT90CAN32/64/128
External Memory Control Register A – XMCRA
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used. Note that
when the XMEM interface is disabled, the address space above the internal SRAM boundary is
not mapped into the internal SRAM.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait-states are configured by the SRW11 and SRW10 bits.
Table 4-3.
Note:
Bit
Read/Write
Initial Value
SRL2
0
0
0
0
1
1
1
1
1. See
Sector limits with different settings of SRL2..0
SRE
R/W
Table 4-1 on page 18
7
0
SRL1
0
0
1
1
0
0
1
1
SRL2
R/W
6
0
SRL0
SRL1
R/W
5
0
0
1
0
1
0
1
0
1
for “XMem start” setting.
SRL0
R/W
4
0
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
Lower sector
Upper sector
SRW11
R/W
Sector
3
0
SRW10
R/W
2
0
SRW01
R/W
1
0
Table 4-3
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
“XMem start”
SRW00
R/W
0
0
Addressing
0xC000 - 0xFFFF
0xA000 - 0xFFFF
0xE000 - 0xFFFF
0x2000 - 0xFFFF
0x4000 - 0xFFFF
0x6000 - 0xFFFF
0x8000 - 0xFFFF
and
N/A
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XMCRA
Figure
- 0xDFFF
- 0xBFFF
7679H–CAN–08/08
- 0xFFFF
- 0x1FFF
- 0x3FFF
- 0x5FFF
- 0x7FFF
- 0x9FFF
4-4. By
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