ATAM893T-TKS Atmel, ATAM893T-TKS Datasheet - Page 52

• Manufacturer Part Number: ATAM893T-TKS
• Description: IC MON TIRE-PRESS ATARX9X SER
• Manufacturer: Atmel
• Series: MARC4r

Specifications of ATAM893T-TKS

• Core Processor: MARC4
• Core Size: 4-Bit
• Speed: 4MHz
• Connectivity: SSI (2-Wire, 3 Wire)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 16
• Ram Size: 256 x 4
• Voltage - Supply (vcc/vdd): 1.8 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

52
ATAM893-D
Timer 3 – Mode 8:
The two compare registers are used for generating two different time intervals. The SSI internal
data output (SO) selects which compare register is used for the output frequency generation. A
'0' level at the SSI data output enables the compare register 1. A '1' level enables compare reg-
ister 2. The compare- and compare mode registers must be programmed to generate the two
frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of
Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2
counter is driven by the Counter 3 (TOG3) (see section “Combination Mode 13”).
Figure 5-31. FSK Modulation
Timer 3 – Mode 9:
The two compare registers are used for generating two different time intervals. The SSI internal
data output (SO) selects which compare register is used for the output pulse generation. In this
mode both compare- and compare mode registers must be programmed for generating the two
pulse widths. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2
is used as baud-rate generator and for the trigger restart of Timer 3. The SSI must be supplied
with a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see
section “Combination Mode 7”).
Figure 5-32. Pulse-width Modulation
Counter 3
Counter 3
TOG2
CM31
CM32
CM31
CM32
SCO
T3R
T3O
T3R
T3O
SIR
SO
SO
0 0 0 0 0 0 0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3
FSK Modulation with Shift Register Data (SO)
Pulse-width Modulation with the Shift Register
0
0
0 0 0 0
0
0 0 0 0 0 1 2 3 4 5 6 7 8 910 11 12 13 14 15 0 1 2 3 4 5
4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3
1
1
6 7 8
0
9 11 12
10
13
14
4680C–4BMCU–01/05
15
0
0
1
4 0
2 3
1
4
1