ATAM893T-TKS Atmel, ATAM893T-TKS Datasheet - Page 60
![IC MON TIRE-PRESS ATARX9X SER](/photos/6/91/69198/453-20-ssop_sml.jpg)
ATAM893T-TKS
Manufacturer Part Number
ATAM893T-TKS
Description
IC MON TIRE-PRESS ATARX9X SER
Manufacturer
Atmel
Series
MARC4r
Datasheet
1.ATAM893T-TKS.pdf
(98 pages)
Specifications of ATAM893T-TKS
Core Processor
MARC4
Core Size
4-Bit
Speed
4MHz
Connectivity
SSI (2-Wire, 3 Wire)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (4K x 8)
Program Memory Type
EEPROM
Eeprom Size
64 x 16
Ram Size
256 x 4
Voltage - Supply (vcc/vdd)
1.8 V ~ 6.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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5.3.3.16
5.3.3.17
5.3.4
5.3.4.1
60
ATAM893-D
Synchronous Serial Interface (SSI)
Timer 3 Capture Register
Timer 3 CaPture Register (T3CP) Byte Read
SSI Features
The counter content can be read via the capture register. There are two ways to use the capture
register. In modes 1 and 4, it is possible to read the current counter value directly out of the cap-
ture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3
input or a signal from Timer 2 stores the current counter value into the capture register. This
counter value can be read from the capture register.
First read cycle
Second read cycle
• 2- and 3-wire NRZ
• 2-wire mode (MCL compatible), additional internal 2-wire link for multi-chip
• With Timer 2
• With Timer 3
packaging solutions
– Bi-phase modulation
– Manchester modulation
– Pulse-width demodulation
– Burst modulation
– Pulse-width modulation (PWM)
– FSK modulation
– Bi-phase demodulation
– Manchester demodulation
– Pulse-width demodulation
– Pulse position Demodulation
Bit 7
Bit 3
Bit 6
Bit 2
Low Nibble
High Nibble
Bit 5
Bit 1
Address: 'Beaux — Subaddress: '4'hex
Bit 4
Bit 0
Reset value: xxxxb
Reset value: xxxxb
4680C–4BMCU–01/05
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