ATAM893T-TKS Atmel, ATAM893T-TKS Datasheet - Page 67

• Manufacturer Part Number: ATAM893T-TKS
• Description: IC MON TIRE-PRESS ATARX9X SER
• Manufacturer: Atmel
• Series: MARC4r

Specifications of ATAM893T-TKS

• Core Processor: MARC4
• Core Size: 4-Bit
• Speed: 4MHz
• Connectivity: SSI (2-Wire, 3 Wire)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 16
• Ram Size: 256 x 4
• Voltage - Supply (vcc/vdd): 1.8 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

5.3.4.8
4680C–4BMCU–01/05
SSI Interrupt
Figure 5-44. MCL Bus Protocol 1
Bus not busy (1)
Start data transfer (2)
Stop data transfer (3)
Data valid (4)
Acknowledge
Figure 5-45. MCL Bus Protocol 2
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit
buffer empty or receive buffer full), the end of SSI data telegram or on the falling edge of the
SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed by the Interrupt Function
control bit (IFN). The SSI interrupt is usually used to synchronize the software control of the SSI
and inform the controller of the present SSI status. The Port 4 interrupts can be used together
with the SSI or, if the SSI itself is not required, as additional external interrupt sources. In either
case this interrupt is capable of waking the controller out of sleep mode.
To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Inter-
rupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in
P4CR register.
SC
SD
SC
SD
(1)
Start
condition
Start
(2)
1st Bit
1
Both data and clock lines remain HIGH.
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition.
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
The state of the data line represents valid data when,
after START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
All address and data words are serially transmitted to and
from the device in eight-bit words. The receiving device
returns a zero on the data line during the ninth clock cycle to
acknowledge word receipt.
valid
Data
(4)
n
change
Data
8th Bit
8
valid
Data
(4)
ACK
9
ATAM893-D
condition
Stop
Stop
(3)
(1)
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