ATMEGA2561-16AI Atmel, ATMEGA2561-16AI Datasheet - Page 196
![IC AVR MCU 256K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561-16AI
Manufacturer Part Number
ATMEGA2561-16AI
Description
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 196 of 444
- Download datasheet (10Mb)
2549M–AVR–09/10
Master and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted
from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the
Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave
by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 20-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the minimum low and high periods should be:
Low period: longer than 2 CPU clock cycles.
High period: longer than 2 CPU clock cycles.
ATmega640/1280/1281/2560/2561
SHIFT
ENABLE
196
Related parts for ATMEGA2561-16AI
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![ATMEGA128RFA1-ZU](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA328P-20PU](/images/manufacturer_photos/0/0/78/atmel_tmb.jpg)
Part Number:
Description:
Manufacturer:
Atmel
Datasheet:
![ATMEGA64RZAV-10PU](/photos/14/18/141872/atmega64rzav-10pu_tmb.jpg)
Part Number:
Description:
MCU ATMEGA644/AT86RF230 40-DIP
Manufacturer:
Atmel
Datasheet:
![ATMEGA64RZAPV-10MU](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA644P/AT86RF230 QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA64RZAPV-10AU](/photos/6/70/67042/313-44-tqfp_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA644P/AT86RF230 TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA128RZAV-8AU](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
MCU ATMEGA1281/AT86RF230 64-TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA128RZBV-8AU](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
MCU ATMEGA1280/AT86RF230 100TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA128RZBV-8CU](/photos/6/70/67048/313-100-tqfp_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA1280/AT86RF100-TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA256RZBV-8CU](/photos/6/89/68968/313-100-cbga_tmb.jpg)
Part Number:
Description:
BUNDLE ATMEGA2560V/AT86RF230-ZU
Manufacturer:
Atmel
Datasheet:
![ATMEGA256RZAV-8AU](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer:
Atmel
Datasheet:
![U641B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
![U4082B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
![U4089B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
![U4255BM-M](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet: