ATMEGA2561-16AI Atmel, ATMEGA2561-16AI Datasheet - Page 23
![IC AVR MCU 256K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561-16AI
Manufacturer Part Number
ATMEGA2561-16AI
Description
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7.2.1
7.3
2549M–AVR–09/10
EEPROM Data Memory
Data Memory Access Times
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 7-3.
The ATmega640/1280/1281/2560/2561 contains 4 Kbytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
“Serial Downloading” on page
“Programming the EEPROM” on page 343
Address (HEX)
60 - 1FF
20 - 5F
0 - 1F
FFFF
Address
21FF
2200
200
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
Compute Address
349,
ATmega640/1280/1281/2560/2561
T1
Memory Access Instruction
416 External I/O Registers
“Programming via the JTAG Interface” on page
64 I/O Registers
External SRAM
Internal SRAM
32 Registers
(0 - 64K x 8)
respectively.
(8192 x 8)
Address valid
CPU
T2
cycles as described in
Next Instruction
T3
Figure
7-3.
354, and
23
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