ATMEGA2561-16AI Atmel, ATMEGA2561-16AI Datasheet - Page 281
![IC AVR MCU 256K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561-16AI
Manufacturer Part Number
ATMEGA2561-16AI
Description
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Manufacturer
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25.4.1
2549M–AVR–09/10
Differential Channels
Table 25-1.
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
all single conversions, and the first free running conversion) when CK
same amount of time as a single ended conversion (13 ADC clock cycles from the next pres-
caled clock cycle). A conversion initiated by the user when CK
cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initi-
ated immediately after the previous conversion completes, and since CK
all automatically started (that is, all but the first) Free Running conversions will take 14 ADC
clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the ADC must
be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset
before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the
conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between
each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are
performed. The result from the extended conversions will be valid. See
sion Timing” on page 278
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
ADC Conversion Time
for timing details.
ATmega640/1280/1281/2560/2561
Sample & Hold (Cycles from
Start of Conversion)
1.5/2.5
13.5
ADC2
1.5
2
. A conversion initiated by the user (that is,
ADC2
is high will take 14 ADC clock
ADC2
Conversion Time (Cycles)
“Prescaling and Conver-
ADC2
ADC2
equal to half the ADC
is low will take the
is high at this time,
13/14
13.5
25
13
281
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