ATMEGA2561-16AI Atmel, ATMEGA2561-16AI Datasheet - Page 242
![IC AVR MCU 256K 16MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA2561-16AI
Manufacturer Part Number
ATMEGA2561-16AI
Description
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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23.2.2
23.3
23.3.1
23.3.2
2549M–AVR–09/10
Data Transfer and Frame Format
Electrical Interconnection
Transferring Bits
START and STOP Conditions
The Power Reduction TWI bit, PRTWI bit in
must be written to zero to enable the 2-wire Serial Interface.
As depicted in
age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or
open-collector. This implements a wired-AND function which is essential to the operation of the
interface. A low level on a TWI bus line is generated when one or more TWI devices output a
zero. A high level is output when all TWI devices trim-state their outputs, allowing the pull-up
resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be pow-
ered in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
specifications are presented there, one relevant for bus speeds below 100 kHz, and one valid for
bus speeds up to 400 kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 23-2. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signalled by changing the level of the SDA
line when the SCL line is high.
SDA
SCL
Figure 23-1 on page
ATmega640/1280/1281/2560/2561
Data Stable
“SPI Timing Characteristics” on page
241, both bus lines are connected to the positive supply volt-
Data Change
“PRR0 – Power Reduction Register 0” on page 56
Data Stable
374. Two different sets of
242
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