ATMEGA6490-16AI Atmel, ATMEGA6490-16AI Datasheet - Page 70

IC AVR MCU FLASH 64K 5V 100TQFP

ATMEGA6490-16AI

Manufacturer Part Number
ATMEGA6490-16AI
Description
IC AVR MCU FLASH 64K 5V 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA6490-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA6490-16AI
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA6490-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
70
ATmega329/3290/649/6490
• SS/PCINT8 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit
PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.
Table 13-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-7.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 13-5 on page
and
Overriding Signals for Alternate Functions in PB7:PB4
PB7/OC2A/
PCINT15
0
0
0
0
OC2A ENABLE
OC2A
PCINT15 •
PCIE1
1
PCINT15 INPUT
Table 13-8
relate the alternate functions of Port B to the overriding signals
65. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/OC1B/
PCINT14
0
0
0
0
OC1B ENABLE
OC1B
PCINT14 •
PCIE1
1
PCINT14 INPUT
PB5/OC1A/
PCINT13
0
0
0
0
OC1A ENABLE
OC1A
PCINT13 •
PCIE1
1
PCINT13 INPUT
PB4/OC0A/
PCINT12
0
0
0
0
OC0A ENABLE
OC0A
PCINT12 •
PCIE1
1
PCINT12 INPUT
2552K–AVR–04/11

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