MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 10

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

ColdFire Module Description
1.3.8
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators. The debug unit in the MCF5307 is a compatible upgrade to
the MCF52xx debug module with added flexibility in the breakpoint registers and a new command to view
the program counter (PC).
The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers
(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register),
and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address, data, and
PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to
generate a processor halt or initiate a debug interrupt exception.
The MCF5307’s new interrupt servicing options during emulator mode allow real-time critical interrupt
service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the Version 3 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data,
and branch target addresses defining processor activity at the CPU’s clock rate.
1.3.9
The MCF5307 PLL module is shown in Figure 3.
The PLL module’s three modes of operation are described as follows.
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Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO
from the MCF5307. The core:bus frequency ratio and other MCF5307 configuration information
are sampled during reset.
Normal mode—In normal mode, the input frequency programmed at reset is clock-multiplied to
provide the processor clock (PCLK).
System Debug Interface
PLL Module
DIVIDE[1:0]
FREQ[1:0]
CLKIN
RSTI
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
CLKIN X 4
PLL
Go to: www.freescale.com
Figure 3. PLL Module
Divide
by 2
Divide by 2,
3, or 4
RSTO
PCLK
PSTCLK
BCLKO
MOTOROLA