MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 11

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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1.4
The ColdFire programming model has two privilege levels—supervisor and user. The S bit in the status
register (SR) indicates the privilege level. The processor identifies a logical address that differentiates
between supervisor and user modes by accessing either the supervisor or user address space.
1.4.1
Figure 4 shows the MCF5307 programming model.
MOTOROLA
Reduced-power mode—In reduced-power mode, the PCLK is disabled by executing a sequence
that includes programming a control bit in the system configuration register (SCR) and then
executing the STOP instruction. Register contents are retained in reduced-power mode, so the
system can be reenabled quickly when an unmasked interrupt or reset is detected.
User mode—When the processor is in user mode (SR[S] = 0), only a subset of registers can be
accessed, and privileged instructions cannot be executed. Typically, most application processing
occurs in user mode. User mode is usually entered by executing a return from exception
instruction (RTE, assuming the value of SR[S] saved on the stack is 0) or a MOVE, SR instruction
(assuming SR[S] is 0).
Supervisor mode—This mode protects system resources from uncontrolled access by users. In
supervisor mode, complete access is provided to all registers and the entire ColdFire instruction
set. Typically, system programmers use the supervisor programming model to implement
operating system functions and provide I/O control. The supervisor programming model provides
access to the same registers as the user model, plus additional registers for configuring on-chip
system resources, as described in Section 1.4.3, “Supervisor Registers.”
Exceptions (including interrupts) are handled in supervisor mode.
Programming Model, Addressing Modes, and
Instruction Set
Programming Model
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Programming Model, Addressing Modes, and Instruction Set
11

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