MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 13

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Status register (SR)
Vector base register
(VBR)
Cache configuration
register (CACR)
Access control
registers (ACR0/1)
RAM base address
register (RAMBAR)
Module base address
register (MBAR)
Condition code
register (CCR)
MAC status register
(MACSR)
Accumulator (ACC) General-purpose register used to accumulate the results of MAC operations
Mask register
(MASK)
Programming Model, Addressing Modes, and Instruction Set
1.4.3
Table 2 summarizes the MCF5307 supervisor-level registers.
1.4.4
The ColdFire instruction set supports high-level languages and is optimized for those instructions most
commonly generated by compilers in embedded applications. Section 2.6, “Instruction Set Summary,” in
the MCF5307 User’s Manual provides an alphabetized listing of the ColdFire instruction set opcodes,
supported operation sizes, and assembler syntax. For two-operand instructions, the first operand is generally
the source operand and the second is the destination.
Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports
most of the common 68K opcodes. A majority of the instructions are binary compatible or optimized 68K
opcodes. This feature, when coupled with the code conversion tools from third-party developers, generally
minimizes software porting issues for customers with 68K applications.
13
Register
Register
Supervisor Registers
Instruction Set
The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous
operation and are used for conditional instruction execution.
Defines the operating configuration of the MAC unit and contains indicator flags from the results of
MAC instructions.
General-purpose register provides an optional address mask for MAC instructions that fetch
operands from memory. It is useful in the implementation of circular queues in operand memory.
The upper byte of the SR provides interrupt information in addition to a variety of mode indicators
signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as
shown in Figure 4.
Defines the upper 12 bits of the base address of the exception vector table used during exception
processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1 Mbyte
address.
Defines the operating modes of the Version 4 cache memories. Control fields configuring the
instruction, data, and branch cache are provided by this register, along with the default attributes
for the 4-Gbyte address space.
Define address ranges and attributes associated with various memory regions within the 4-Gbyte
address space. Each ACR defines the location of a given memory region and assigns attributes
such as write-protection and cache mode (copyback, write-through, cacheability). Additionally,
CACR fields assign default attributes to the instruction and data memory spaces.
Provide the logical base address for the 4-Kbyte SRAM module and define attributes and access
types allowed for the SRAM.
Defines the logical base address for the memory-mapped space containing the control registers for
the on-chip peripherals.
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 1. User-Level Registers (continued)
Table 2. Supervisor-Level Registers
Go to: www.freescale.com
Description
Description
MOTOROLA

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