MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 7

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1.3.1.3
The MAC unit provides signal processing capabilities for the MCF5307 in a variety of applications
including digital audio and servo control. Integrated as an execution unit in the processor’s OEP, the MAC
unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input
operands are supported by this design in addition to a full set of extensions for signed and unsigned integers,
plus signed, fixed-point fractional input operands.
1.3.1.4
Integrated into the OEP, the divide module performs operations using signed and unsigned integers. The
module supports word and longword divides producing quotients and/or remainders.
1.3.1.5
The MCF5307 architecture includes an 8-Kbyte unified cache. This four-way, set-associative cache
provides pipelined, single-cycle access on cached instructions and operands.
As with all ColdFire caches, the cache controller implements a non-lockup, streaming design. The use of
processor-local memories decouples performance from external memory speeds and increases available
bandwidth for external devices or the on-chip 4-channel DMA.
The cache implements line-fill buffers to optimize 16-byte line burst accesses. Additionally, the cache
supports copyback, write-through, or cache-inhibited modes. A 4-entry, 32-bit buffer is used for cache line
push operations and can be configured for deferred write buffering in write-through or cache-inhibited
modes.
1.3.1.6
The 4-Kbyte on-chip SRAM module provides pipelined, single-cycle access to memory regions mapped to
these devices. The memory can be mapped to any 0-modulo-32K location in the 4-Gbyte address space. The
SRAM module is useful for storing time-critical functions, the system stack, or heavily-referenced data
operands.
1.3.2
The MCF5307 DRAM controller provides a direct interface for up to two blocks of DRAM. The controller
supports 8-, 16-, or 32-bit memory widths and can easily interface to PC-100 DIMMs. A unique addressing
scheme allows for increases in system memory size without rerouting address lines and rewiring boards.
The controller operates in normal mode or in page mode and supports SDRAMs and EDO DRAMs.
1.3.3
The MCF5307 provides four fully programmable DMA channels for quick data transfer. Dual- and
single-address modes support bursting and cycle steal. Data transfers are 32 bits long with packing and
unpacking supported along with an auto-alignment option for efficient block transfers. Automatic block
transfers from on-chip serial UARTs are also supported through the DMA channels.
MOTOROLA
DRAM Controller
DMA Controller
MAC Module
Integer Divide Module
8-Kbyte Unified Cache
Internal 4-Kbyte SRAM
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
ColdFire Module Description
7