MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 9

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

need occasional bursts of rapid communication over short distances among several devices. The I
operate in master, slave, or multiple-master modes.
1.3.7
The MCF5307 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM, ROM, and
peripheral devices through the use of fully programmable chip selects and write enables. Support for burst
ROMs is also included. Through the on-chip PLL, users can input a slower clock (16.6 to 45 MHz) that is
internally multiplied to create the faster processor clock (33.3 to 90 MHz).
1.3.7.1
The bus interface controller transfers information between the ColdFire core or DMA and memory,
peripherals, or other devices on the external bus. The external bus interface provides up to 32 bits of address
bus space, a 32-bit data bus, and all associated control signals. This interface implements an extended
synchronous protocol that supports bursting operations.
Simple two-wire request/acknowledge bus arbitration between the MCF5307 processor and another bus
master, such as an external DMA device, is glueless with arbitration logic internal to the MCF5307
processor. Multiple-master arbitration is also available with some simple external arbitration logic.
1.3.7.2
Eight fully programmable chip select outputs support the use of external memory and peripheral circuits
with user-defined wait-state insertion. These signals interface to 8-, 16-, or 32-bit ports. The base address,
access permissions, and internal bus transfer terminations are programmable with configuration registers for
each chip select. CS0 also provides global chip select functionality of boot ROM upon reset for initializing
the MCF5307.
1.3.7.3
A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin
basis.
1.3.7.4
The interrupt controller provides user-programmable control of ten internal peripheral interrupts and
implements four external fixed interrupt-request pins. Each internal interrupt can be programmed to any one
of seven interrupt levels and four priority levels within each of these levels. Additionally, the external
interrupt request pins can be mapped to levels 1, 3, 5, and 7 or levels 2, 4, 6, and 7. Autovector capability is
available for both internal and external interrupts.
1.3.7.5
To help with system diagnostics and manufacturing testing, the MCF5307 processor includes dedicated
user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability, often
referred to as the Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a
standard.
MOTOROLA
System Interface
External Bus Interface
Chip Selects
16-Bit Parallel Port Interface
Interrupt Controller
JTAG
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
ColdFire Module Description
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