MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 6

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

ColdFire Module Description
1.2.1
The MCF5307 is manufactured in a 0.35-µ CMOS process with triple-layer-metal routing technology. This
process combines the high performance and low power needed for embedded system applications. Inputs
are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0.5 V to
GND - 0.5 V, with guaranteed TTL-level specifications.
1.3
The following sections provide overviews of the various modules incorporated in the MCF5307.
1.3.1
The Version 4 ColdFire core consists of two independent and decoupled pipelines to maximize
performance—the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP).
1.3.1.1
The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the operand execution
pipeline (OEP). Because the fetch and execution pipelines are decoupled by a eight-instruction FIFO buffer,
the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the
time stalled waiting for instructions. To maximize the performance of branch instructions, the Version 3 IFP
implements a branch prediction mechanism. Backward branches are predicted to be taken. The prediction
for forward branches is controlled by a bit in the Condition Code Register (CCR). These predictions allow
the IFP to redirect the fetch stream down the path predicted to be taken well in advance of the actual
instruction execution. The result is significantly improved performance.
1.3.1.2
The prefetched instruction stream is gated from the FIFO buffer into the two-stage OEP. The OEP consists
of a traditional two-stage RISC compute engine with a register file access feeding an arithmetic/logic unit
(ALU). The OEP decodes the instruction, fetches the required operands and then executes the required
function.
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On-chip PLL
— Supports processor clock/bus clock ratios of 66/33, 66/22, 66/16.5, 90/45, 90/30, and 90/22.5
— Supports low-power mode
Product offerings
— 75 Dhrystone 2.1 MIPS at 90 MHz
— Implemented in 0.35 µ, triple-layer-metal process technology with 3.3-V operation (5.0-V
— 208-pin plastic QFP package
— 0°–70° C operating temperature
ColdFire Module Description
compliant I/O pads)
Process
ColdFire Core
Instruction Fetch Pipeline (IFP)
Operand Execution Pipeline (OEP)
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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