MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 3

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and
on-chip memories, are integrated using advanced process technologies.
The MCF5307 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and
ColdFire customers in which development tools and customer code can be leveraged. In fact, customers
moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K
assembly code to the ColdFire architecture.
Based on the concept of variable-length RISC technology, the ColdFire family combines the architectural
simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In defining
the ColdFire architecture for embedded processing applications, a 68K-code compatible core combines
performance advantages of a RISC architecture with the optimum code density of a streamlined,
variable-length M68000 instruction set.
By using a variable-length instruction set architecture, embedded system designers using ColdFire RISC
processors enjoy significant advantages over conventional fixed-length RISC architectures. The denser
binary code for ColdFire processors consumes less memory than many fixed-length instruction set RISC
processors available. This improved code density means more efficient system memory use for a given
application and allows use of slower, less costly memory to help achieve a target performance level.
The MCF5307 is the first standard product to implement the Version 3 ColdFire microprocessor core. To
reach higher levels of frequency and performance, numerous enhancements were made to the V2
architecture. Most notable are a deeper instruction pipeline, branch acceleration, and a unified cache, which
together provide 75 (Dhrystone 2.1) MIPS at 90 MHz. Increasing the internal speed of the core also allows
higher performance while providing the system designer with an easy-to-use lower speed system interface.
The processor complex frequency is an integer multiple, 2 to 4 times, of the external bus frequency. The core
clock can be stopped to support a low-power mode.
Serial communication channels are provided by an I
UARTs. Four channels of DMA allow for fast data transfer using a programmable burst mode independent
of processor execution. The two 16-bit general-purpose multimode timers provide separate input and output
signals. For system protection, the processor includes a programmable 16-bit software watchdog timer. In
addition, common system functions such as chip selects, interrupt control, bus arbitration, and an
IEEE 1149.1 JTAG module are included. A sophisticated debug interface supports background-debug mode
plus real-time trace and debug with expanded flexibility of on-chip breakpoint registers. This interface is
present in all ColdFire standard products and allows common emulator support across the entire family of
microprocessors.
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The following list summarizes MCF5307 features:
MOTOROLA
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ColdFire processor core
— Variable-length RISC, clock-multiplied Version 3 microprocessor core
— Fully code compatible with Version 2 processors
— Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and
— Eight-instruction FIFO buffer provides decoupling between the pipelines
— Branch prediction mechanisms for accelerating program execution
— 32-bit internal address bus supporting 4 Gbytes of linear address space
MCF5307 Features
two-stage operand execution pipeline (OEP)
MCF5307 Integrated Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
2
C interface module and two programmable full-duplex
MCF5307 Features
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