C8051F330 Silicon Laboratories Inc, C8051F330 Datasheet - Page 132

• Manufacturer Part Number: C8051F330
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F330

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F330/1, C8051F330D
132
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1-0:
ENSMB
R/W
Bit7
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-
itors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to .
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is con-
figured to Split Mode, only the High Byte of the timer is held in reload while SCL is high.
Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt
service routine should reset SMBus communication.
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
SMBCS1-SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 15.1.
SMBCS1
INH
R/W
Bit6
0
0
1
1
Figure 15.5. SMB0CF: SMBus Clock/Configuration Register
SMBCS0
BUSY
Bit5
R
0
1
0
1
EXTHOLD SMBTOE SMBFTE SMBCS1
R/W
Bit4
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Rev. 1.2
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
SMBCS0 00000000
R/W
Bit0
0xC1
Reset Value