C8051F330 Silicon Laboratories Inc, C8051F330 Datasheet - Page 36

• Manufacturer Part Number: C8051F330
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F330

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F330/1, C8051F330D
5.1.
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: Ports0-1, the on-chip temperature sensor, or the positive power supply (
following may be selected as the negative input: Ports0-1, VREF, or GND. When GND is selected as the
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in
Figure 5.5 and Figure .
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST.
When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are
measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left-
justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from -VREF to VREF x 511/512. Example codes are shown below for both right-justi-
fied and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1). To force the Crossbar to skip a Port
pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1). See
on page 113
36
VREF x 1023/1024
–VREF x 256/512
VREF x 512/1024
VREF x 256/1024
VREF x 256/512
VREF x 511/512
Input Voltage
Input Voltage
Analog Multiplexer
–VREF
0
0
for more Port I/O configuration details.
Right-Justified ADC0H:ADC0L
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
(AD0LJST = 0)
0xFC00
0x01FF
0xFF00
0x0100
0x0000
0x03FF
0x0200
0x0100
0x0000
Rev. 1.2
Left-Justified ADC0H:ADC0L
Left-Justified ADC0H:ADC0L
Section “14. Port Input/Output”
(AD0LJST = 1)
(AD0LJST = 1)
0x7FC0
0xFFC0
0xC000
0x4000
0x0000
0x8000
0x8000
0x4000
0x0000
V
DD ). Any of the