C8051F330 Silicon Laboratories Inc, C8051F330 Datasheet - Page 51

• Manufacturer Part Number: C8051F330
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F330

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6. 10-Bit Current Mode DAC (IDA0, C8051F330 and C8051F330D only)
The C8051F330 and C8051F330D device includes a 10-bit current-mode Digital-to-Analog Converter
(IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5
mA, 1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register
(see Figure 6.3). When IDA0EN is set to ‘0’, the IDAC port pin (P0.1) behaves as a normal GPIO pin.
When IDA0EN is set to ‘1’, the digital output drivers and weak pull-up for the IDAC pin are automatically
disabled, and the pin is connected to the IDAC output. An internal bandgap bias generator is used to gen-
erate a reference current for the IDAC whenever it is enabled. When using the IDAC, bit 1 in the P0SKIP
register should be set to ‘1’, to force the Crossbar to skip the IDAC pin.
6.1.
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and sup-
ports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output
updates on a write to IDA0H, on a Timer overflow, or on an external pin edge.
6.1.1. Update Output On-Demand
In its default mode (IDA0CN.[6:4] = ‘111’) the IDA0 output is updated “on-demand” on a write to the high-
byte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode,
and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the
IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data reg-
isters. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be
IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by
initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see
information on the format of the 10-bit IDAC data word within the 16-bit SFR space).
IDA0 Output Scheduling
IDA0OMD1
IDA0OMD0
IDA0CM2
IDA0CM1
IDA0CM0
IDA0EN
8
2
Figure 6.1. IDA0 Functional Block Diagram
10
C8051F330/1, C8051F330D
Rev. 1.2
IDA0
Section 6.2
IDA0
for
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