MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 28

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1
Electrical Characteristics
4.3.5.1
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
timing parameters.
28
Values provided where applicable.
tcable1
tcable2
tskew1
tskew2
tskew3
tskew4
tskew5
tskew6
Name
ti_ds
ti_dh
tsui
tbuf
tco
tsu
thi
T
Bus clock period (ipg_clk_ata)
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Hold time ata_iordy edge to ata_data (UDMA-in only)
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
Set-up time ata_data to bus clock L-to-H
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data
(read)
Max buffer propagation delay
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Max difference in cable propagation delay without accounting for ground bounce
Timing Parameters
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Table 24. ATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Table 24
Freescale Semiconductor
Contributing Factor
peripheral clock
transceiver
transceiver
transceiver
frequency
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
15 ns
10 ns
cable
cable
cable
cable
cable
shows ATA
7 ns
5 ns
4 ns
7 ns
1