MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet - Page 64

• Manufacturer Part Number: MCIMX31LVKN5
• Description: IC MPU MAP I.MX31L 457-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX31r

Specifications of MCIMX31LVKN5

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, POR, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.22 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 457-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Tdicd
Electrical Characteristics
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 50
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.”
images correspond to straight polarity of the Sharp signals.
64
Tdicu
Display interface clock down time
Display interface clock up time
DISPB_D3_DATA
=
DISPB_D3_SPL
DISPB_D3_CLS
DISPB_D3_REV
=
DISPB_D3_PS
DISPB_D3_CLK
1
-- - T
2
DISPB_D3_HSYNC
1
-- - T
2
HSP_CLK ceil
depicts the Sharp HR-TFT panel interface timing, and
HSP_CLK ceil
⋅
Figure 50. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
⋅
2 DISP3_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
2 DISP3_IF_CLK_UP_WR
--------------------------------------------------------------------- -
⋅
⋅
HSP_CLK_PERIOD
HSP_CLK_PERIOD
SPL pulse width is fixed and aligned to the first data of the line.
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
REV toggles every HSYNC period.
IP24
IP22
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Horizontal timing
IP21
IP23
IP25
D1 D2
IP26
1 DISPB_D3_CLK period
Table 49
D320
lists the timing parameters. The
Freescale Semiconductor
The timing