XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 16

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

XR17C158
5V PCI BUS OCTAL UART
.
F
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
P
IGURE
RIORITY
N+2
Bit
x
1
2
3
4
5
6
7
Channel-7
N+1
4. T
Bit
B
Bit
HE
N
IT
[
0
0
0
0
1
1
1
1
N
INT3 Register
G
N+2
+2]
Bit
LOBAL
Channel-6
N+1
Bit
B
IT
I
T
[
Bit
NTERRUPT
N
0
0
1
1
0
0
1
1
N
ABLE
+1]
N+2
Bit
T
ABLE
Channel-5
5: UART C
N+1
Bit
B
IT
0
1
0
1
0
1
0
1
R
6: UART C
[
N
EGISTER
Bit
N
]
N+2
Bit
None
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only within channel 0, reserved in other channels.
TIMER Time-out. Available only within channel 0, reserved in other chan-
nels.
HANNEL
Channel-4
INT0, INT1, INT2 and INT3
, INT0, INT1, INT2
N+1
Bit
HANNEL
Interrupt Registers,
INT2 Register
Bit
N
[7:0] I
N+2
Bit
16
[7:0] I
Channel-3
NTERRUPT
N+1
Bit
NTERRUPT
Bit
N
AND
N+2
I
Bit
NTERRUPT
S
Channel-2
INT3
OURCE
Ch-7 Ch-6 Ch-5 Ch-4
N+1
Bit-7
Bit
C
LEARING
Bit-6
Bit
N
E
S
NCODING
OURCE
Bit-5
N+2
Bit
Channel-1
INT0 Register
Bit-4
N+1
INT1 Register
Bit
(
S
)
Ch-3 Ch-2 Ch-1 Ch-0
Bit-3
Bit
N
N+2
Bit-2
Bit
xr
Channel-0
N+1
Bit-1
Bit
Bit-0
Bit
N
REV. 1.4.3