XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 67

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

xr
REV. 1.4.3
5.0 PROGRAMMING EXAMPLES ............................................................................................................. 54
ABSOLUTE MAXIMUM RATINGS .................................................................................. 55
ELECTRICAL CHARACTERISTICS................................................................................ 55
PACKAGE DIMENSIONS ................................................................................................ 63
T
ABLE OF
DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING................................................................. 55
AC ELECTRICAL CHARACTERISTICS
R
4.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 32
4.5 INFRARED MODE .......................................................................................................................................... 34
4.6 INTERNAL LOOPBACK ................................................................................................................................. 35
4.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING ....................................... 36
4.8 REGISTERS .................................................................................................................................................... 39
IER versus Receive FIFO Interrupt Mode Operation................................................................................................. 39
IER versus Receive/Transmit FIFO Polled Mode Operation ..................................................................................... 39
5.1
EVISION
F
F
T
F
F
F
T
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
4.3.3 RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ........................................................................... 31
4.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 39
4.8.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 39
4.8.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE................................................................ 39
4.8.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE.......................................................................................... 39
4.8.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY............................................................................................ 40
4.8.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY.................................................................................................. 42
4.8.7 LINE CONTROL REGISTER (LCR) - READ/WRITE.................................................................................................. 44
4.8.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE ........................................................................................... 45
4.8.9 LINE STATUS REGISTER (LSR) - READ/ONLY ....................................................................................................... 46
4.8.10 MODEM STATUS REGISTER (MSR) - READ-ONLY .............................................................................................. 47
4.8.11 MODEM STATUS REGISTER (MSR) - WRITE-ONLY ............................................................................................. 48
4.8.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE................................................................................................. 49
4.8.13
4.8.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE..................................................................................... 50
4.8.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ-ONLY ......................................................................... 52
4.8.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE-ONLY ........................................................................ 52
4.8.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ-ONLY............................................................................ 52
4.8.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE-ONLY............................................................................ 52
UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS .................. 54
10: A
11: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 37
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
13: I
14: T
15: P
16: A
17: 16 S
18: S
19: UART RESET CONDITIONS...................................................................................................................................... 53
12. R
13. R
14. A
15. I
16. I
17. PCI B
18. D
19. D
20. D
21. 5V PCI B
22. T
23. R
H
C
ISTORY
ONTENTS
NTERRUPT
FEATURE CONTROL REGISTER (FCTR) - READ/WRITE.................................................................................... 49
UTO
RANSMIT AND
ARITY SELECTION
UTO
OFTWARE
NFRARED
NTERNAL
RANSMIT
ECEIVER
ECEIVER
UTO
EVICE
EVICE
EVICE
ECEIVE
ELECTABLE
RTS/CTS
RS485 H
US
RTS/DTR
...................................................................................................................................... 64
C
C
C
D
C
ONFIGURATION AND
ONFIGURATION REGISTERS
ONFIGURATION
US
L
T
S
F
D
O
O
ATA
ONFIGURATION
OOP
RANSMIT
OURCE AND
LOW
ATA
PERATION IN NON
PERATION IN
............................................................................................................ I
C
R
ALF
LOCK
H
R
OR
ECEIVE
B
I
YSTERESIS
C
EADY
AND
NTERRUPT AT
........................................................................................................................................................ 45
ACK
-
ONTROL
DUPLEX
DTR/DSR F
(DC
D
CTS/DSR F
................................................................................................................................................. 35
ATA
I
FIFO T
NTERRUPT AT
P
R
FIFO
TO
RIORITY
S
EGISTERS
E
D
F
PACE
L
NCODING AND
UNCTIONS
33MH
IRECTION
-FIFO M
EVELS
UART R
RIGGER
AND
T
LOW
RIGGER
R
L
LOW
Z
EVEL
EGISTERS
FOR
, UART R
F
, UART R
) .......................................................................................................................... 61
W
C
LOW
T
ODE
EGISTERS
C
HEN
ONTROL
........................................................................................................................ 51
L
RIGGER
C
EVEL
ONTROL
..................................................................................................................... 41
ONTROL
L
5V SIGNALING .................................................................. 56
EVEL
C
.................................................................................................................. 31
R
T
ONTROL
ECEIVE
RIGGER
R
S
EGISTERS AND
EGISTERS AND
S
L
EAD AND
........................................................................................................... 62
ELECTION
EVEL
R
ELECTION
D
O
EAD
ELAY FROM
II
PERATION
D
M
T
ATA
................................................................................................. 62
ABLE
ODE
O
W
PERATION FOR A
............................................................................................ 43
D
.......................................................................................... 32
RITE OPERATION
......................................................................................... 31
-D
ECODING
T
...................................................................................... 33
R
T
IS
RANSMIT
ECEIVE
RANSMIT
S
ELECTED
.......................................................................... 34
D
D
HADED BITS ARE ENABLED BY
-
ATA
TO
ATA
B
................................................................. 57
YTE OR
-R
................................................................ 50
B
B
ECEIVE
URST
URST
DWORD ...................................... 58
R
W
................................................. 48
EAD
RITE
O
PCI BUS OCTAL UART
O
PERATION
PERATION
EFR B
........................ 60
..................... 59
IT
XRT99L00
-4. ....... 38