XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 25

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

xr
REV. 1.4.3
The XR17C158 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), ....., 0xF80 (channel 7). The
entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD
reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following
tables show this clearly.
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2),
............, 0xD00 (channel 6) and 0xF00 (channel 7).
3.1.2
3.1.3
Data Bit-31
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
Write n+0 to n+3
Write n+4 to n+7
PCI Bus
R
PCI Bus
W
EAD
B7 B6 B5 B4 B3 B2 B1 B0
RITE
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Etc.
RX FIFO,
Etc
Receive Data Byte n+3
TX FIFO
Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, 0x780, 0x980, 0xB80,
0xD80, 0xF80
Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700, 0x900, 0xB00, 0xD00, 0xF00
E
RRORS
Channel 0 to 7 Receive Data with Line Status Register in a 32-bit alignment through the Configuration
Channel 0 to 7 ReceiveData in 32-bit alignment through the Configuration Register Address
Register Address 0x0180, 0x0380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80
FIFO Data n+1
FIFO Data n+3
FIFO Data n+3
FIFO Data n+7
B
B
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
Line Status Register n+1
Receive Data Byte n+2
3
3
FIFO Data n+2
FIFO Data n+6
LSR n+1
LSR n+3
B
B
YTE
YTE
25
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+1
Receive Data Byte n+0
FIFO Data n+0
FIFO Data n+2
FIFO Data n+1
FIFO Data n+5
B
B
YTE
YTE
1
1
5V PCI BUS OCTAL UART
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+0
Line Status Register n+0
FIFO Data n+0
FIFO Data n+4
LSR n+0
LSR n+2
B
B
YTE
YTE
XR17C158
Data Bit-0
PCI Bus
0
Data Bit-0
0
PCI Bus