XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 66

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

XRT99L00
PCI BUS OCTAL UART
GENERAL DESCRIPTION .................................................................................................1
PIN DESCRIPTIONS .........................................................................................................3
FUNCTIONAL DESCRIPTION ...........................................................................................7
1.0 XR17C158 REGISTERS .........................................................................................................................8
2.0 CRYSTAL OSCILLATOR / BUFFER ...................................................................................................23
3.0 TRANSMIT AND RECEIVE DATA .......................................................................................................24
4.0 UART ....................................................................................................................................................27
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................ 8
1.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................. 10
3.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ............................................... 24
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 27
4.2 TRANSMITTER ............................................................................................................................................... 28
4.3 RECEIVER ...................................................................................................................................................... 30
F
F
F
T
T
T
T
F
T
T
F
T
F
F
F
T
F
T
F
F
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
IGURE
ABLE
ABLE
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
IGURE
1.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 15
1.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
1.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 18
1.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 18
1.2.5 RESET [23:16] (DEFAULT 0X00)............................................................................................................................... 18
1.2.6 SLEEP [31:24] - (DEFAULT 0X00)............................................................................................................................. 19
1.2.7 DEVICE IDENTIFICATION AND REVISION ............................................................................................................... 19
1.2.8 REGB REGISTER ....................................................................................................................................................... 20
1.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS .............................................................................................................. 20
1.2.10 MPIO REGISTER ...................................................................................................................................................... 20
3.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, AND
3.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, 0X780, 0X980, 0XB80, 0XD80, 0XF80
3.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, 0XF00 .......... 25
4.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 28
4.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 28
4.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 29
4.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 29
4.3.1
4.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 31
8-BIT FORMAT ............................................................................................................................................... 26
1: PCI L
2: XR17C158 D
3: D
4: D
5: UART C
6: UART C
7: TIMER CONTROL R
8: T
9: T
1. B
2. P
3. T
4. T
5. T
6. M
7. T
8. E
9. B
10. T
11. T
00-00).............................................................................................................................................................................. 17
0XF00 ............................................................................................................................................................................. 24
25
.....................................................................................................................................................1
RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ........................................................................................... 30
RANSMIT AND
YPICAL DATA RATES WITH A
EVICE
EVICE
HE
HE
IMER
YPICAL OSCILLATOR CONNECTIONS
LOCK
IN
XTERNAL
AUD
ULTIPURPOSE INPUT
................................................................................................................................................1
RANSMITTER
RANSMITTER
O
XR17C158 R
OCAL
G
UT OF THE
/C
R
LOBAL
C
C
D
HANNEL
HANNEL
ATE
OUNTER CIRCUIT
ONFIGURATION
ONFIGURATION
IAGRAM
B
C
US
G
EVICE
LOCK
I
NTERRUPT
R
ENERATOR
.................................................................................................................................2
C
ECEIVE
O
O
[7:0] I
[7:0] I
D
............................................................................................................................................................. 1
ONFIGURATION
PERATION IN NON
PERATION IN
C
EVICE
EGISTER
C
ONNECTION FOR
ONFIGURATION
EGISTERS
/
NTERRUPT
NTERRUPT
OUTPUT INTERNAL CIRCUIT
D
R
R
.................................................................................................................................................. 2
R
............................................................................................................................................... 17
ATA
............................................................................................................................................... 27
EGISTERS SHOWN IN
EGISTERS SHOWN IN
EGISTER
S
14.7456 MH
ETS
R
FIFO
TABLE OF CONTENTS
...................................................................................................................................... 17
EGISTER IN
S
S
C
..................................................................................................................................... 8
PACE
OURCE
LEARING
-FIFO M
, INT0, INT1, INT2
............................................................................................................................... 23
R
AND
E
EGISTERS
XTENDED
R
Z CRYSTAL OR EXTERNAL CLOCK AT
F
EGISTERS
E
LOW
B
................................................................................................................... 16
ODE
NCODING
YTE FORMAT
BYTE
DWORD
............................................................................................................. 11
C
............................................................................................................ 29
D
........................................................................................................... 21
ONTROL
ATA
......................................................................................................... 9
..................................................................................................... 16
I
ALIGNMENT
R
AND
ATE
ALIGNMENT
, 16C550
M
INT3 .................................................................................. 16
.......................................................................................... 23
ODE
................................................................................... 14
................................................................................... 30
COMPATIBLE
............................................................................... 14
16X S
............................................................ 26
AMPLING
.......................................... 28
xr
REV. 1.4.3