XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 31

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

xr
REV. 1.4.3
F
4.3.2
4.3.3
IGURE
Receive Data
Byte and Errors
16X or 8X Sampling
Clock (8XMODE Reg.)
F
IGURE
13. R
64 bytes by 11-
bit wide FIFO
Receiver Operation in non-FIFO Mode
Receiver Operation in FIFO and Flow Control Mode
(8XMODE Register)
and Errors
Data Byte
16X or 8X Clock
12. R
Receive
ECEIVER
ECEIVER
O
PERATION IN
O
Receive Data Shift
Register (RSR)
PERATION IN NON
LSR bits
Flags in
Error
Receive Data
4:2
Receive
(64-byte)
FIFO
FIFO
Data
Receive Data Shift
Register (RSR)
Holding Register
AND
Receive Data
-FIFO M
(RHR)
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
LOW
Data Bit
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
C
31
ONTROL
ODE
Validation
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Data Bit
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
M
ODE
RHR Interrupt (ISR bit-2)
Receive Data Characters
Receive Data Characters
5V PCI BUS OCTAL UART
RXFIFO1
XR17C158
RXFIFO1